The present invention relates to a PLL (Phase Locked Loop) circuit for a digital display apparatus, and, more particularly, to a PLL circuit which can avoid, as much as possible, disturbance of an image at the time the PLL circuit is unlocked and locked in.
For digital display apparatuses, such as a PDP (Plasma Display Panel) apparatus and an LCD (Liquid Crystal Display) apparatus, which internally carry out digital processing in accordance with a horizontal sync signal and a vertical sync signal, both supplied in an analog form, and an image signal having a predetermined timing based on those sync signals, an internal system clock signal which is synchronous with the horizontal sync signal or the like is generated by using a PLL circuit.
An input analog image signal is sampled and converted to a digital signal by using a system clock signal whose frequency is K times the frequency of the horizontal sync signal generated by a PLL circuit and an internal sync signal or a comparison signal, which is the system clock signal frequency-divided by K, and an image is displayed via individual drive circuits of the display panel. This can allow the internal sync signal and system clock signal, phase synchronous with the horizontal sync signal, to be completely synchronized to each other at the time of locking, so that an image signal can be accurately sampled and displayed.
Briefly speaking, an ordinary PLL circuit, which will be discussed in detail later, compares an input external horizontal sync signal with a variable horizontal sync signal as a comparison signal by means of a phase comparator, generates from the obtained phase difference a voltage corresponding to the phase difference by means of an integrator (low-pass filter), and controls a voltage controlled oscillator (VCO) with this voltage to thereby generate a system clock signal synchronous with the external horizontal sync signal. This system clock signal is frequency-divided by an integer number and the resultant signal is fed back to the phase comparator as the variable horizontal sync signal of the comparison signal. This feedback loop controls the VCO in accordance with the phase difference, so that a system clock signal synchronous with the external horizontal sync signal can always be generated stably.
However, when a TV channel is switched or switching between a video mode and a TV mode is performed, or when the mode is switched to a multi-scan mode on the monitor side, for example, the phase of the input horizontal sync signal or vertical sync signal is changed, and a phase difference is produced between the external horizontal sync signal and comparison signal immediately after switching, setting the PLL circuit in an unlocked state. Of course, the voltage controlled oscillator (VCO) in the PLL circuit changes and controls the frequency of the system clock according to the phase difference to carry out lock-in, but until such lock-in is implemented, the lock-off state continues, causing a phenomenon like rolling of images on the display screen.
As a solution to this shortcoming, some approaches have been proposed, such as outputting no image on the screen when lock-off occurs. However, blackening the screen, even temporarily, is not a preferable solution.
An external horizontal sync signal in a composite image signal which is output from a home VTR or the like includes a skew deviated from the normal period according to, for example, the VHS standards. Further, an extra pulse or the like may be added to the external horizontal sync signal for some other reasons. When such a skew pulse or added pulse occurs, a large phase difference with respect to the comparison signal is detected. When a pulse is added in a midway, for example, a deviation of 180 degrees is detected. Further, the skew itself causes a significant phase difference.
When such a large phase difference is detected, the control voltage according to that phase difference becomes greater than the control range exceeding the lock range, and goes off the control range of the VCO, so that the unlocked state continues for a long time. During that period, the system clock that should be output becomes asynchronous with the external horizontal sync signal, disturbing images. Although a PLL circuit is originally so designed as to follow up a slight variation in the external horizontal sync signal, the aforementioned occurrence of a large phase variation is not anticipated. With respect to the occurrence of a skew pulse or an added pulse, therefore, it takes a long time to implement lock-in from the unlocked state.
It is therefore an object of the present invention to provide a PLL circuit which can output an optimal internal sync signal even when lock-off of a PLL circuit in a digital display apparatus occurs.
It is another object of this invention to provide a digital display apparatus which can prevent an undesirable phenomenon like rolling of images even in an unlocked state.
It is a further object of this invention to provide a PLL circuit which does not have an unstable operation even when a skew pulse or an extra pulse occurs.
According to this invention, the above objects are achieved by a phase locked loop circuit for a digital display apparatus for outputting a clock signal whose frequency is a multiple of a frequency of a horizontal sync signal to be supplied by an integer number, and feeding back a comparison signal whose frequency is the clock signal frequency-divided by the integer number to thereby generate the clock signal phase-synchronous with the horizontal sync signal, which circuit comprises:
a lock/unlock detection circuit for comparing phases of the horizontal sync signal and the comparison signal to detect a locked state and an unlocked state of the phase locked loop circuit; and
an internal sync signal generation circuit for outputting the comparison signal inside as an internal sync signal when the locked state is detected by the lock/unlock detection circuit and outputting the horizontal sync signal as the internal sync signal when the unlocked state is detected.
With this structure, as an internal sync signal which becomes a reference internal horizontal sync signal, the comparison signal is used in a locked state and the horizontal sync signal that is externally supplied is used in an unlocked state. Since the external horizontal sync signal which keeps a phase relationship with an image signal even in an unlocked state including a lock-in state is directly used as the internal horizontal sync signal, therefore, it is possible to prevent a phenomenon like rolling of images on the screen.
According to this invention, the above objects are achieved by a digital display apparatus for receiving from outside a external horizontal sync signal, a external vertical sync signal and an analog image signal having a predetermined timing based on the external sync signals, generating a digital image signal inside and displaying an image, which apparatus comprises:
a phase locked loop circuit for outputting a clock signal whose frequency is a multiple of a frequency of the horizontal sync signal by an integer number, and feeding back a comparison signal whose frequency is the clock signal frequency-divided by the integer number to thereby generate the clock signal phase-synchronous with the horizontal sync signal;
a generation circuit for generating an internal horizontal sync signal based on the comparison signal when the phase locked loop circuit is in a locked state, and generating the internal horizontal sync signal based on the external horizontal sync signal when the phase locked loop circuit is in an unlocked state;
an analog-to-digital converter for sampling the analog image signal in accordance with the clock signal, thereby generating the digital image signal; and
a display unit for displaying the image in accordance with the digital image signal and the internal horizontal sync signal.
According to this invention, the above objects are achieved by a PLL (Phase Locked Loop) circuit for a display apparatus for generating a clock signal synchronous with an external sync signal in an image signal to be supplied, which comprises:
a phase comparator for comparing phases of a reference signal including the external sync signal and a comparison signal and generating an output according to the phase difference therebetween;
an oscillator for controlling a frequency of the clock signal of output in accordance with the phase difference;
a frequency divider for frequency-dividing the clock signal by an integer number to thereby generate the comparison signal;
a skew detector for detecting occurrence of a skew, in which the phase in the external sync signal is deviated from a normal period, to reset the frequency divider.
The skew detector generates a dummy pulse upon detection of the sync signal being not generated even when the normal period has elapsed, and further synthesizes the external sync signal and the dummy pulse, thereby generating the reference signal.
The skew detector resets the phase comparator upon detection of occurrence of the skew.
With this structure, even when a skew occurs in an external sync signal, the counter of the frequency divider in the PLL circuit is reset, causing the comparison signal to be likewise generated in association with the skew, so that the occurrence of the skew does not produce a large phase difference between the external sync signal and the comparison signal. The PLL circuit can therefore maintain the lock-in state.
Even when the external sync signal is shifted toward a longer period, a dummy pulse is generated and is synthesized with the external sync signal, so that an unlocked state originated from pulse drop-out can be avoided. Further, because the phase comparator is reset immediately upon occurrence of a skew, the PLL circuit does not go unlocked even when a dummy pulse overlaps the skewed external sync signal.
It is desirable that the above PLL circuit is used for a digital display apparatus, such as a PDP or LCD.